A hardware-efficient FIR architecture with input-data and tap folding

In this work, by using input-data and tap folding, a hardware-efficient FIR architecture is developed with a high folding number. To further minimize hardware complexity of an FIR architecture using the radix-4 Booth algorithm, 2-bit sub-data are utilized to replace the conventional 3-bit sub-data in order to reduce the number of input sub-data latches required in the input-data flow. Additionally, a tree accumulation with simplified carry-in bit processing is designed to reduce the hardware complexity of the accumulation path. With folding in input data and tap number of the architecture, and reduction in hardware complexity for the input sub-data latches and accumulation path, the proposed FIR architecture demonstrates a low hardware complexity. By using the TSMC 0.25 μm CMOS technology, the proposed radix-4 Booth algorithm FIR architecture with 10-bit input data and filter coefficient to accomplish 128-tap filter operations not only satisfies the throughput-rate demand of the conventional architectures, it also saves 65% to 73% of the area occupied.