Thermal challenges to gate length reduction of FET

The constant need for higher speed continues to lead to devices with shorter gate lengths, smaller gate widths, and gate finger spacing. The relationship of between various transistor parameters and the device lifetime is unclear due to the complexity of the problem, and the difficulty and expense of measuring reliability. This paper presents an analytical expression relating the reliability to a field effect transistor´s (FET) gate length, based on thermal considerations. Experimental observations support the model´s conclusions.