Class-AB rail-to-rail CMOS analog buffer

Author

Carrillo, Juan M. ; Duque-Carrillo, J. Francisco ; Torralba, Antonio ; Carvajal, Ramón G.

Author_Institution

Dept. of Electron. & Elec. Eng., Univ. de Extremadura, Badajoz, Spain

fYear

2005

fDate

23-26 May 2005

Firstpage

1008

Abstract

In this paper, a low-power rail-to-rail CMOS analog buffer is presented. The circuit is based on an input stage made up of two complementary class AB differential pairs, while a simple additional circuit allows rail-to-rail operation at the output terminal. The proposed circuit combines low static power consumption and high drive capability, hence is very suitable for applications with large capacitive loads. The buffer has been designed in a 0.35-μm CMOS technology to operate with a ±1.5 V dual supply. Simulated results are provided in order to demonstrate the proper operation of the proposed circuit. A rail-to-rail signal swing is achieved and a THD lower than -44 dB is obtained for a 2.4-V_pp 100-kHz input sinewave signal, whereas the input capacitance is lower than 32 fF.

Keywords

CMOS analogue integrated circuits; buffer circuits; current mirrors; low-power electronics; 0.35 micron; 1.5 V; 100 kHz; 2.4 V; 3 V; 32 fF; CMOS analog buffer; analog voltage buffers; class-AB analog buffer; current mirrors; high drive capability; input capacitance reduction; input rail-to-rail operation; large capacitive load driving; low-power buffer; output rail-to-rail operation; parallel connected complementary differential pairs; rail-to-rail signal swing; CMOS technology; Circuit simulation; Circuit testing; Energy consumption; Parasitic capacitance; Rail to rail inputs; Rail to rail operation; Signal design; Variable structure systems; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on

Print_ISBN

0-7803-8834-8

Type

conf

DOI

10.1109/ISCAS.2005.1464761

Filename

1464761