DocumentCode
3542488
Title
Efficient implementation of trace-back unit in a reconfigurable Viterbi decoder fabric
Author
Zhan, Cheng ; Khawam, Sami ; Arslan, Tughrul ; Lindsay, Iain
Author_Institution
Sch. of Electron. & Eng., Edinburgh Univ., UK
fYear
2005
fDate
23-26 May 2005
Firstpage
1048
Abstract
This paper presents a reconfigurable Viterbi fabric with efficient track-back unit in a system on chip device. The proposed reconfigurable fabric can support Viterbi implementations with constraint lengths ranging from 3 to 9, and code rates in the range 1/2-1/3. Our results illustrate that the proposed architecture has superior power consumption and throughput characteristics compared with a generic field programmable gate array (FPGA) and a digital signal processor (DSP), respectively.
Keywords
Viterbi decoding; power consumption; reconfigurable architectures; system-on-chip; power consumption; reconfigurable Viterbi decoder fabric; system on chip device; throughput characteristics; trace-back unit; Application specific integrated circuits; Convolutional codes; Digital signal processing; Energy consumption; Fabrics; Field programmable gate arrays; Maximum likelihood decoding; System-on-a-chip; Throughput; Viterbi algorithm;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on
Print_ISBN
0-7803-8834-8
Type
conf
DOI
10.1109/ISCAS.2005.1464771
Filename
1464771
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