Parallel FFT computation with a CDMA-based network-on-chip

Author

Kim, Daewook ; Kim, Manho ; Sobelman, Gerald E.

Author_Institution

Dept. of Electr. & Comput. Eng., Minnesota Univ., USA

fYear

2005

fDate

23-26 May 2005

Firstpage

1138

Abstract

Fast Fourier transform (FFT) algorithms are used in a wide variety of digital signal processing applications and many of these require high-performance parallel implementations. We present two methodologies for mapping an FFT computation onto a CDMA-based star topology network-on-chip (NoC) architecture. These implementations reduce the FFT data shuffling time and simplify the data flow between processing elements. The design has been modeled using SystemC and the simulation results provide throughput and latency performance metrics for the different mapping scenarios.

Keywords

code division multiple access; data flow computing; digital signal processing chips; fast Fourier transforms; integrated circuit design; logic design; network topology; parallel architectures; system-on-chip; CDMA-based network-on-chip; data flow; data shuffling time; digital signal processing; fast Fourier transform algorithms; multiprocessor system-on-chip; parallel FFT computation; parallel processing; star topology network-on-chip architecture; Computational modeling; Computer architecture; Computer networks; Concurrent computing; Digital signal processing; Fast Fourier transforms; Network topology; Network-on-a-chip; Signal processing algorithms; Throughput;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on

Print_ISBN

0-7803-8834-8

Type

conf

DOI

10.1109/ISCAS.2005.1464794

Filename

1464794