A 0.18 μm CMOS transceiver design for high-speed backplane data communications

An 8 Gb/s current mode logic (CML) transmitter with multi-tap FIR pre-emphasis has been implemented in 0.18 μm CMOS technology and verified to operate with PRBS7 data over a 34 inch FR4 backplane. A half-rate clock retiming circuit for generating symbol-spaced data is proposed to alleviate the speed requirement of the traditional full-rate clock retiming. At the receive side, a frequency and phase-locked clock and data recovery (CDR) circuit incorporates a multiphase voltage-controlled oscillator (VCO) and a half-rate bang-bang phase/frequency detector (PFD) with embedded data retiming. The total power dissipation of the transceiver is 75 mW at a 1.8 V supply.