ESD protection circuit design for ultra-sensitive IO applications in advanced sub-90nm CMOS technologies

Author

Mergens, Markus ; Wybo, Geert ; Van Camp, Benjamin ; Keppens, Bart ; De Ranter, Frederic ; Verhaege, Koen ; Jozwiak, Phil ; Armer, John ; Russ, Christian

Author_Institution

Sarnoff Eur., Aalter, Belgium

fYear

2005

fDate

23-26 May 2005

Firstpage

1194

Abstract

This paper presents a protection strategy for ultra-sensitive I/O containing thin gate oxides, while combining two complementary ESD design approaches: (1) low-voltage diode-chain triggered SCR clamps that allow for efficient voltage clamping; (2) active-source-pump circuits applied for effective expansion of narrow ESD design windows for ultra-thin GOX protection. The focus of the paper is on the ASP schemes while some RF aspects are covered as well.

Keywords

CMOS integrated circuits; electrostatic discharge; integrated circuit reliability; low-power electronics; thyristors; ESD protection circuit; RF aspects; active-source-pump circuits; advanced sub-90nm CMOS technologies; low-voltage diode-chain triggered SCR clamps; narrow ESD design windows; thin gate oxides; ultra-sensitive I/O applications; ultra-thin GOX protection; voltage clamping; Application specific processors; CMOS technology; Circuit synthesis; Clamps; Diodes; Electrostatic discharge; Protection; Radio frequency; Thyristors; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on

Print_ISBN

0-7803-8834-8

Type

conf

DOI

10.1109/ISCAS.2005.1464807

Filename

1464807