DocumentCode
3542758
Title
On-chip ESD protection for RF I/Os: devices, circuits and models
Author
Rosenbaum, Elyse ; Hyvonen, Sami
Author_Institution
Dept. of Electr. & Comput. Eng., Illinois Univ., Urbana, IL, USA
fYear
2005
fDate
23-26 May 2005
Firstpage
1202
Abstract
ESD protection circuits load RF I/O pads. The negative effect on RF performance can be limited by careful construction and layout of the protection devices. The cancellation technique extends the range of frequencies for which the protection circuit has an acceptably small effect on RF performance.
Keywords
CMOS integrated circuits; electrostatic discharge; integrated circuit layout; integrated circuit reliability; radiofrequency integrated circuits; ESD protection circuits; RF I/O pads; RF performance; cancellation technique; layout; on-chip ESD protection; Biological system modeling; Capacitance; Circuits; Electrostatic discharge; Impedance matching; Low-noise amplifiers; Operating systems; Protection; Radio frequency; Stress;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on
Print_ISBN
0-7803-8834-8
Type
conf
DOI
10.1109/ISCAS.2005.1464809
Filename
1464809
Link To Document