Compact model of a CBRAM cell in Verilog-A

CBRAMs (Conductive Bridging Random Access Memory) are a kind of Resistive Random Access Memories (RRAMs) fabricated in the BEOL (Back-End-Of-Line). They are a promising breakthrough for including permanent retention mechanisms (non-volatility) in embedded systems at low cost. Thus, they are becoming very interesting for the designers community as well. To use this device to design innovative circuits, a compact model is mandatory. In this paper, we propose a continuous physical compact model, written in Verilog-A. Main advantage of this approach is its robustness compared to macromodel approach. Moreover, our approach provides more flexibility compared to a behavioural model for adding multilevel aspect. The model is calibrated with the characterization results and integrated in Cadence design flow using Eldo simulator.