Combined 2-D transform and quantization architectures for H.264 video coders

Author

Lin, Heng-Yao ; Chao, Yi-Chih ; Chen, Che-Hong ; Liu, Bin-Da ; Yang, Jar-Ferr

Author_Institution

Dept. of Electr. Eng., Nat. Cheng Kung Univ., Tainan, Taiwan

fYear

2005

fDate

23-26 May 2005

Firstpage

1802

Abstract

In this paper, the low-complexity hardware architectures of 4×4 forward and inverse transforms with integrated quantizer and dequantizer for H.264 advanced video coders (AVC) are proposed. By applying the regularity of the quantization matrix, the quantization can be merged into the transform step, which results in a reduction of the hardware complexity in VLSI implementation. The proposed integrated transforms have been synthesized with TSMC 0.35 μm technology. Simulation results show that it can achieve 256 M samples/sec at 32 MHz in the encoder part and 448 M samples/sec at 56 MHz in the decoder part.

Keywords

Hadamard transforms; VLSI; discrete cosine transforms; quantisation (signal); video coding; 0.35 micron; 32 MHz; 56 MHz; AVC; DCT; H.264 video coders; Hadamard transforms; VLSI implementation; combined 2D transform/quantization architectures; decoder; dequantizer; encoder; integrated quantizer; inverse transforms; quantization matrix regularity; Arithmetic; Automatic voltage control; Chaos; Decoding; Discrete cosine transforms; Discrete transforms; Hardware; Quadratic programming; Quantization; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on

Print_ISBN

0-7803-8834-8

Type

conf

DOI

10.1109/ISCAS.2005.1464959

Filename

1464959