Simple yet effective algorithms for block and I/O buffer placement in flip-chip design

We study the problem of block and I/O buffer placement in flip-chip design. The goal of the problem is to minimize simultaneously the total path delay and the total skew of all input/output signals. We present two simple, yet effective, algorithms for the problem. Both algorithms place blocks to minimize the total path delay, and place I/O buffers to minimize the total skew. As compared to an existing method (Peng, C.-Y., 2003), the experimental results show that both algorithms are able to get better placement solutions with improvement rates of up to 65% and 77.5%, respectively, and run much faster.