An ultra-low-voltage MTCMOS/SIMOX gate array

Author

Urano, Masami ; Douseki, Takakuni ; Hatano, Takahiro ; Fukuda, Hideki ; Harada, Mitsuru ; Tsuchiya, Toshiaki

Author_Institution

NTT Syst. Electron. Labs., Kanagawa, Japan

fYear

1997

fDate

7-10 Sep 1997

Firstpage

7

Lastpage

11

Abstract

An ultra-low-voltage gate array has been developed using a multi-threshold CMOS (MTCMOS) circuit and separation by implanted oxygen (SIMOX) technology, which is a type of a silicon-on-insulator (SOI) technology. A 250-K basic-cell gate array was fabricated using 0.25-μm MTCMOS/SIMOX technology. The gate delay time is 140 ps at 1.2 V and 470 ps at 0.5 V. A 30-KG test circuit was fabricated and the same operating speed as that of 0.5-μm at 3.3 V (i.e., 25 MHz) was obtained at 0.58 V with the power consumption reduced to 1/100. At 0.76 V, the operating speed was 40 MHz

Keywords

CMOS logic circuits; SIMOX; logic arrays; 0.5 micron; 0.5 to 1.2 V; 140 to 470 ps; 25 to 40 MHz; MTCMOS/SIMOX gate array; Si; multithreshold CMOS circuit; power consumption reduction; ultra-low-voltage gate array; CMOS technology; Circuit testing; Delay effects; Digital signal processing chips; Energy consumption; Logic gates; MOSFETs; Silicon on insulator technology; Switches; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC Conference and Exhibit, 1997. Proceedings., Tenth Annual IEEE International

Conference_Location

Portland, OR

ISSN

1063-0988

Print_ISBN

0-7803-4283-6

Type

conf

DOI

10.1109/ASIC.1997.616968

Filename

616968