DocumentCode
3544418
Title
Low-voltage high-performance switched current memory cell
Author
Handkiewicz, Andrzej ; Sniatala, Pawel ; Lukowiak, Marcin
Author_Institution
Fac. of Electr. Eng., Poznan Tech. Univ., Poland
fYear
1997
fDate
7-10 Sep 1997
Firstpage
12
Lastpage
16
Abstract
A new switched current (SI) memory cell is proposed in the paper. Analysis and simulations show very good properties of the cell. Layout of a sample and hold (SH) circuit composed of the memory cell is also presented. This SH circuit is a basic cell of bilinear integrators and delay lines, being components of one- and two-dimensional SI filters. The method and tools for automated design of such filters are briefly described
Keywords
analogue storage; circuit CAD; sample and hold circuits; switched current circuits; switched filters; SH circuit; SI memory cell; automated design; bilinear integrators; delay lines; low-voltage operation; one-dimensional SI filters; sample/hold circuit; switched current memory cell; two-dimensional SI filters; Analytical models; Circuit simulation; Clocks; Delay lines; Diodes; Filters; Image processing; MOS devices; Software libraries; Switches;
fLanguage
English
Publisher
ieee
Conference_Titel
ASIC Conference and Exhibit, 1997. Proceedings., Tenth Annual IEEE International
Conference_Location
Portland, OR
ISSN
1063-0988
Print_ISBN
0-7803-4283-6
Type
conf
DOI
10.1109/ASIC.1997.616969
Filename
616969
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