3D IC implementation for MPSOC architectures: Mesh and butterfly based NoC

In the CMOS technologies below 65 nm the wire delay dominates the gate delay. 3D IC design is one solution to deal with this problem. We propose in this work to implement two different MPSOC architectures based on Mesh and Butterfly NoC topologies. We use the 3D IC technology from the Tezzaron Company. Thanks to its symmetry, the mesh based NoC architecture is easier to implement compared to the other one based on the Butterfly NoC. In fact with this one, we have to deal with additional problems like mapping and partitioning. With its long links, the Butterfly architecture is a better example than the mesh topology to prove the efficiency of 3D design.