• DocumentCode
    3544608
  • Title

    Power awareness for multi-voltage island X-clock tree construction with double-via insertion

  • Author

    Tsai, Chia-Chun ; Lee, Trong-Yen

  • Author_Institution
    Dept. of Comput. Sci. & Inf. Eng., Nanhua Univ., Chiayi, Taiwan
  • fYear
    2012
  • fDate
    10-11 July 2012
  • Firstpage
    168
  • Lastpage
    173
  • Abstract
    This paper proposes an algorithm to construct an X-clock tree with double via insertion that connects several voltage islands for power minimization. We first construct the X-clock tree for each voltage island and make double via insertion for this tree to improve yield and reliability. Then we combine these X-clock trees based on a well-defined connection with inserted level shifters to reduce power. The delay effect due to total number of vias is also accounted. Experimental results show that X-clock tree based on multi-voltage islands has 22.46% and 5.41% respectively in power and delay less than that of single voltage island.
  • Keywords
    circuit reliability; clocks; delays; minimisation; delay effect; double-via insertion; level shifter insertion; multivoltage island X-clock tree construction; power awareness; power minimization; reliability; single voltage island; Capacitance; Clocks; Delay; Metals; Minimization; Power demand; Wires; Xclock tree; double via insertion; level shifter; multi-voltage island; power consumption;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Quality Electronic Design (ASQED), 2012 4th Asia Symposium on
  • Conference_Location
    Penang
  • Print_ISBN
    978-1-4673-2687-2
  • Type

    conf

  • DOI
    10.1109/ACQED.2012.6320495
  • Filename
    6320495