Timing-driven global routing with efficient buffer insertion

Timing optimization is an important goal of global routing in the deep submicron era. To guarantee the timing performance of the circuit, merely adopting topology optimization becomes inadequate. We present an efficient timing-driven global routing algorithm with buffer insertion. Our approach is capable of applying topological-based timing optimization and buffer insertion simultaneously with routability considerations. Compared with previous work, we efficiently solve the timing issues under a limited buffer usage. Experimental results have demonstrated significant delay improvement within a short runtime with a very small number of buffers inserted.