DocumentCode
3545984
Title
High-speed Parallel 32×32-b Multiplier Using a Radix-16 Booth Encoder
Author
Ping-hua, Chen ; Juan, Zhao
Author_Institution
Fac. of Comput., Guangdong Univ. of Technol., Guangzhou, China
fYear
2009
fDate
21-22 Nov. 2009
Firstpage
406
Lastpage
409
Abstract
A 32 × 32-b high-speed parallel multiplier is proposed in this paper. The new multiplier uses a Radix-16 Booth Encoder, uses a mixed compressed tree constituted by 4-2 and 5-2 compressor and an improved 64-bit carry-look ahead adder (CLA) which combines the characteristics of CSS and CLA. The test result shows that, compared with iterative multiplier, this multiplier has some improvement on performance.
Keywords
adders; digital arithmetic; encoding; multiplying circuits; trees (mathematics); 4-2 compressor; 5-2 compressor; carry-lookahead adder; high-speed parallel 32x32-b multiplier; mixed compressed tree; radix-16 booth encoder; Algorithm design and analysis; Application software; Cascading style sheets; Concurrent computing; Digital signal processing; Encoding; Hardware; Information technology; Iterative algorithms; Signal processing algorithms; Compressor; Multiplier; Radix-16 Booth Encoder;
fLanguage
English
Publisher
ieee
Conference_Titel
Intelligent Information Technology Application Workshops, 2009. IITAW '09. Third International Symposium on
Conference_Location
Nanchang
Print_ISBN
978-1-4244-6420-3
Electronic_ISBN
978-1-4244-6421-0
Type
conf
DOI
10.1109/IITAW.2009.44
Filename
5419596
Link To Document