Automatic monitor generation from regular expression based specifications for module interface verification

In order to verify module interfaces, various verification methods have been proposed. This paper focuses on monitor-based verification of module interfaces. Monitor circuits are usually described by hand. This is a very hard task, however, since it requires low-level design of circuits or state machines. If specifications of module interfaces are described in more a comprehensive way, and monitor circuits are generated by the description, we can verify module interfaces more efficiently. In our method, first, we describe specifications of module interfaces in a language based on regular expressions, then construct behavior models from the description. Finally, we generate a monitor circuit. The circuit connects to a verification target to check whether interface behaviors of the target satisfy the specification. If interface behaviors violate the specification, the circuit asserts an error signal. In this paper, we state the method, and show a verification example based on simulation in which FSM state coverage is monitored.