DocumentCode
3547214
Title
High voltage tolerant output buffer design for mixed voltage interfaces
Author
Mandal, Debashis ; Mandal, Pradip
Author_Institution
Indian Inst. of Technol., Kharagpur, India
fYear
2005
fDate
23-26 May 2005
Firstpage
4277
Abstract
This paper presents the design of a mixed voltage 3.3V/5.5V CMOS output buffer. The proposed design technique eliminates gate-oxide overstress and output to supply current flow when common bus voltage is higher than the supply voltage. While this paper discusses the 3.3V/5.5V supply combination as an example, the same circuit topology can be used for other mixed supply combination like 2.5V/5V, 1.8V/3.3V.
Keywords
CMOS integrated circuits; buffer circuits; network topology; 3.3 V; 5.5 V; CMOS output buffer; circuit topology; high voltage tolerant output buffer; mixed voltage interfaces; Atherosclerosis; CMOS technology; Circuit topology; Current supplies; Driver circuits; Latches; Leakage current; MOS devices; Tunneling; Voltage control;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on
Print_ISBN
0-7803-8834-8
Type
conf
DOI
10.1109/ISCAS.2005.1465576
Filename
1465576
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