A 10-bit 400-MS/s 170 mW 4-times interleaved A/D converter in 0.35-μm BiCMOS

Author

Riikonen, Jaana ; Aho, Mikko ; Hakkarainen, Väinö ; Halonen, Kari ; Sumanen, Lauri

Author_Institution

Electron. Circuit Design Lab., Helsinki Univ. of Technol., Finland

fYear

2005

fDate

23-26 May 2005

Firstpage

4622

Abstract

A time-interleaved four-channel pipeline analog-to-digital converter is presented. The A/D converter utilizes a double-sampling, low power, high speed operational amplifier. The maximum sample rate of the converter is 400 MS/s. With a 3.3 V supply voltage, a power consumption of 170 mW is achieved. The circuit is designed with a 0.35 μm BiCMOS process and for a full-scale 147.7 MHz input the spurious-free-dynamic-range is 47.8 dB.

Keywords

BiCMOS integrated circuits; analogue-digital conversion; operational amplifiers; pipeline processing; 0.35 micron; 147.7 MHz; 170 mW; 3.3 V; BiCMOS; converter maximum sample rate; double-sampling opamp; four-channel pipeline A/D converter; high speed operational amplifier; low power operational amplifier; pipeline analog-to-digital converter; spurious-free-dynamic-range; time-interleaved pipeline ADC; BiCMOS integrated circuits; Calibration; Delay lines; Energy consumption; Operational amplifiers; Pipelines; Power supplies; Sampling methods; Signal resolution; Threshold voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on

Print_ISBN

0-7803-8834-8

Type

conf

DOI

10.1109/ISCAS.2005.1465662

Filename

1465662