Efficient multi-prime RSA immune against hardware fault attack

Author

Yang, Y. ; Abid, Z. ; Wang, W. ; Zhang, Z. ; Yang, C.

Author_Institution

Dept. of Electr. & Comput. Eng., Univ. of Western Ontario, London, Ont., Canada

fYear

2005

fDate

23-26 May 2005

Firstpage

4649

Abstract

In this paper, a study on the factorization analysis and improvement of the Chinese remainder theorem (CRT)-based multi-prime RSA against the hardware fault attack is carried out. A novel immune CRT-based multi-prime RSA is proposed and its properties in terms of the factorization complexity and operation speed are compared with those of the extended CRT-2 protocol (S. Yen et al, IEEE Trans. on computers, vol.52, p.461-472, 2003). The proposed multi-prime RSA and the extended CRT-2 protocol applied in a three-prime RSA are implemented using FPGA technology. The implementation results show that the proposed immune multi-prime RSA is 30% faster while requiring only 75% of the hardware resources, compared to the extended CRT-2 RSA protocol.

Keywords

field programmable gate arrays; public key cryptography; CRT; Chinese remainder theorem; FPGA implementation; cryptosystems; extended CRT-2 protocol; factorization analysis; factorization complexity; hardware fault attack immunity; immune multiprime RSA; public key cryptography; Authentication; Cathode ray tubes; Cryptographic protocols; Data security; Field programmable gate arrays; Hardware; IP networks; Information analysis; Public key; Public key cryptography;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on

Print_ISBN

0-7803-8834-8

Type

conf

DOI

10.1109/ISCAS.2005.1465669

Filename

1465669