Energy-saving design technique achieved by latched pass-transistor adiabatic logic

In recent years, low power circuit design has been an important issue in system on chip (SoC) and VLSI design areas. Adiabatic logics, which dissipate less power than static CMOS logic, have been introduced as a promising new approach in low power circuit design. It is expected that adiabatic logic will be a substitute for static CMOS logic especially for the purpose of low power applications. Despite the proposal of several adiabatic logic families, no research has been done on the technique for replacing CMOS circuits with adiabatic logic. In this paper, we propose a latched pass-transistor adiabatic logic (LPAL) and an energy-saving design scheme for low power applications. LPAL replaces CMOS circuits, providing more energy-efficiency than other forms of adiabatic logic. In simulation, we compared the energy consumption of pass-transistor adiabatic logic (PAL), a good model for conventional adiabatic logics, with that of LPAL. Simulation results show that the LPAL circuit results in power savings of 44% over PAL.