DocumentCode
3547479
Title
Multiple project wafers for medium-volume IC production
Author
Wu, Meng-Chiou ; Lin, Rung-Bin
Author_Institution
Comput. Sci. & Eng. Dept., Yuan-Ze Univ., Chung-li, Taiwan
fYear
2005
fDate
23-26 May 2005
Firstpage
4725
Abstract
The multi-project wafer (MPW) is commonly used for low-volume IC production. In this paper, we study whether it can be used for medium-volume production. Cost equations are developed to compute the cut-off volume of each chip. We find that the MPW approach is viable for medium-volume production. The study can be extended to decide whether a given set of projects should go with MPW and whether to include a project into or remove a project from an MPW program.
Keywords
costing; integrated circuit layout; integrated circuit manufacture; MPW; chip cut-off volume; cost equations; fabrication cost model; mask cost sharing; medium-volume IC production; multiple project wafers; reticle floorplanning; wafer dicing; Chip scale packaging; Computer science; Costs; Electronic design automation and methodology; Equations; Fabrication; Field programmable gate arrays; Foundries; Production; Semiconductor device modeling;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on
Print_ISBN
0-7803-8834-8
Type
conf
DOI
10.1109/ISCAS.2005.1465688
Filename
1465688
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