DocumentCode
3547618
Title
Convergent micro-pipelines: a versatile operator for mixed asynchronous-synchronous computations
Author
Gies, Valentin ; Bernard, Thierry M. ; Mérigot, Alain
Author_Institution
ENSTA, Paris, France
fYear
2005
fDate
23-26 May 2005
Firstpage
5242
Abstract
Micro-pipelines are linear (1D) structures for asynchronous communications. In retinotopic VLSI vision chips, communicating over 2D image regions is a key to efficient mid-level vision computations. However, micro-pipelines are limited to 1D communications only. In this paper, we introduce an extension of the micro-pipeline, called the convergent micro-pipeline, for implementing mixed asynchronous-synchronous regional computations over arbitrary shaped regions. This operator is exploited in programmable artificial retinas (PAR), that is, image sensors with a digital processor in each pixel, for low power vision applications. To illustrate the behavior and versatility, several regional computations are described.
Keywords
VLSI; asynchronous circuits; computer vision; image sensors; low-power electronics; pipeline processing; 2D image regions; convergent micro-pipelines; image sensors; linear 1D structures; low power vision; mid-level vision computations; mixed asynchronous-synchronous computations; pixel digital processor; programmable artificial retinas; retinotopic VLSI vision chips; Asynchronous communication; Clocks; Communication networks; Computer vision; Image converters; Image sensors; Microprocessors; Pixel; Retina; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on
Print_ISBN
0-7803-8834-8
Type
conf
DOI
10.1109/ISCAS.2005.1465817
Filename
1465817
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