DocumentCode
3547674
Title
A scalable DCO design for portable ADPLL designs
Author
Wu, Chia-Tsun ; Wang, Wei ; Wey, I-Chyn ; Wu, An-Yeu
Author_Institution
Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
fYear
2005
fDate
23-26 May 2005
Firstpage
5449
Abstract
A novel digital controlled oscillator (DCO) design methodology is presented in this paper. The new design methodology includes a scalable DCO architecture and the developed design flow. With precise analysis in early stage, the design effort of DCO can be reduced significantly. The proposed DCO architecture has the characteristics of high resolution, flexible operating range, and easy design. The design is suitable for a high performance clock generator in a system on chip (SoC) application.
Keywords
clocks; digital control; digital phase locked loops; system-on-chip; SoC; digital controlled oscillator; flexible operating range; high performance clock generator; high resolution architecture; portable ADPLL design; scalable DCO design; system on chip; Circuits; Clocks; Delay; Design methodology; Inverters; Libraries; Phase frequency detector; Phase locked loops; System-on-a-chip; Voltage-controlled oscillators;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on
Print_ISBN
0-7803-8834-8
Type
conf
DOI
10.1109/ISCAS.2005.1465869
Filename
1465869
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