DocumentCode
3547719
Title
Delay modeling of CMOS/CPL logic circuits
Author
Wan, Yunazhong ; Shams, Maitham
Author_Institution
Dept. of Electron., Carleton Univ., Ottawa, Ont., Canada
fYear
2005
fDate
23-26 May 2005
Firstpage
5613
Abstract
Effective optimization methods aimed at achieving maximal speeds in single-technology logic circuits are widely available but systematic ways suitable for circuits involving mixtures of logic families are not. The combination of standard CMOS with CPL (complementary pass-transistor logic) is examined with an eye to finding the best structure and the best insertion points for CMOS buffers intended to improve a CPL chain´s propagation time and drive capability.
Keywords
CMOS logic circuits; MOS logic circuits; buffer circuits; circuit optimisation; integrated circuit design; logic design; CMOS buffers; CMOS logic circuits; NMOS pass-transistor network; complementary pass-transistor logic circuits; cross-coupled PMOS transistors; optimization methods; single-technology logic circuits; CMOS logic circuits; Capacitance; Degradation; Delay effects; Latches; Logic circuits; MOS devices; MOSFETs; Semiconductor device modeling; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on
Print_ISBN
0-7803-8834-8
Type
conf
DOI
10.1109/ISCAS.2005.1465910
Filename
1465910
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