BDD decomposition for mixed CMOS/PTL logic circuit synthesis

Logic synthesis plays a major role in design automation. A logic function can be represented by a binary decision diagram (BDD). In this paper, we propose a technique to construct a BDD whose nodes can be implemented by CMOS logic and pass-transistor logic (PTL) in a cell library. The conventional synthesis flow needs three cell libraries: CMOS cell library, PTL cell library, and CMOS remapping pattern. To simplify the synthesis flow, we decompose the logic function to two kinds of functions and map them to PTL and CMOS cells, respectively. The cell library contains high speed cells and low power cells. The experimental results show that our approach has better performance and uses less area than conventional CMOS technology mappings.