Estimating likelihood of correctness for error candidates to assist debugging faulty HDL designs

Author

Jiang, Tai-Ying ; Liu, Chien-Nan Jimmy ; Jou, Jing-Yang

Author_Institution

Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan

fYear

2005

fDate

23-26 May 2005

Firstpage

5682

Abstract

Debugging priority is a helpful technique to assist debugging faulty HDL designs. However, the debugging priority obtained by confidence score sorting is not good enough due to the inaccuracy in estimating the likelihood of correctness for error candidates. Therefore, we developed the refined confidence score for deriving better debugging priority.

Keywords

fault diagnosis; hardware description languages; logic design; logic testing; confidence score sorting; debugging priority; design error correction; design error diagnosis; error candidate correctness likelihood estimation; faulty HDL design debugging; refined confidence score; Circuit faults; Circuit simulation; Computer bugs; Debugging; Design engineering; Error correction; Explosions; Hardware design languages; Sorting; Testing;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on

Print_ISBN

0-7803-8834-8

Type

conf

DOI

10.1109/ISCAS.2005.1465927

Filename

1465927

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3547737