Low complexity, high speed decoder architecture for quasi-cyclic LDPC codes

Author

Wang, Zhongfeng ; Jia, Qing-Wei

Author_Institution

Sch. of Electr. Eng. & Comput. Sci., Oregon State Univ, Corvallis, CA, USA

fYear

2005

fDate

23-26 May 2005

Firstpage

5786

Abstract

This paper presents a low complexity, very high speed decoder architecture for quasi-cyclic low density parity check (QC-LDPC) codes, specifically Euclidian geometry (EG) based QC-LDPC codes. Algorithmic transformation and architectural level optimizations are employed to increase the clock speed. Enhanced partially parallel decoding architectures are proposed to linearly increase the overall throughput with the introduction of a small percentage of extra hardware. Based on the proposed architecture, a FPGA implementation of a (8176, 7154) EG-LDPC decoder can achieve a worst-case throughput of 169 Mbit/s.

Keywords

cyclic codes; decoding; field programmable gate arrays; geometric codes; parallel architectures; parity check codes; 169 Mbit/s; Euclidian geometry based codes; FPGA implementation; QC-LDPC codes; high speed decoder architecture; low complexity decoder architecture; low density parity check codes; partially parallel decoding architectures; quasi-cyclic LDPC codes; Clocks; Decoding; Field programmable gate arrays; Geometry; Hardware; Message passing; Parity check codes; Quantum cascade lasers; Table lookup; Throughput;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on

Print_ISBN

0-7803-8834-8

Type

conf

DOI

10.1109/ISCAS.2005.1465953

Filename

1465953