Parallely testable design for detection of neighborhood pattern sensitive faults in high density DRAMs

The number of test patterns for DRAM increases at least linearly as the memory density increases. It affects the increase in the total cost of memory test. We consider only neighborhood pattern sensitive faults, which are the major and complicated faults in a high density DRAM. Thus, for a 1 G DRAM, the testing time may be several hours if test patterns are applied to memory cells one by one. In order to speed up the testing of high density DRAMs, we propose a parallel accessible decoder, which allows multiple read/write operations at a time. With this scheme, we can reduce the testing time roughly 500 times. This new decoder requires only 8 extra transistors per bit line.