A fast VLSI architecture for full-search variable block size motion estimation in MPEG-4 AVC/H.264

Author

Kim, Minho ; Hwang, Ingu ; Chae, Soo-Ik

Author_Institution

Sch. of Electr. Eng., Seoul Nat. Univ., South Korea

Volume

1

fYear

2005

fDate

18-21 Jan. 2005

Firstpage

631

Abstract

We describe a fast VLSI architecture for full-search motion estimation for the blocks with 7 different sizes in MPEG-4 AVC/H.264. The proposed variable block size motion estimation (VBSME) architecture consists of a 16×16 PE array, an adder tree and comparators to find all 41 motion vectors and their minimum SADs for the blocks of 16×16, 16×8, 8×16, 8×8, 8×4, 4×8 and 4×4. It employs a 2D datapath and its control of the search area data is simple and regular. The proposed VBSME can achieve 100% PE utilization by employing a preload register and a search data buffer inside each PE and allow real-time processing of 4CIF(704×576) video with 15 fps at 100 MHz for a search range of |-32∼+31|.

Keywords

VLSI; code standards; integrated circuit design; motion estimation; video coding; 100 MHz; 2D datapath; 4CIF video; MPEG-4 AVC/H.264; PE array; VLSI architecture; adder tree; comparator; full-search motion estimation; motion vector; preload register; real-time processing; search data buffer; variable block size motion estimation; Automatic voltage control; Computational complexity; Computer architecture; Computer buffers; Electronic mail; MPEG 4 Standard; Motion estimation; Transform coding; Very large scale integration; Video compression;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation Conference, 2005. Proceedings of the ASP-DAC 2005. Asia and South Pacific

Print_ISBN

0-7803-8736-8

Type

conf

DOI

10.1109/ASPDAC.2005.1466240

Filename

1466240