VLSI implementation of a self-checking self-exercising memory system

A VLSI implementation of a design concept for a self-checking self-exercising (SCSE) memory system described by D. Rennels and S. Chau (see Proc. 16th Int. Symp. on Fault-Tolerant Computing p.358-63 (1986)) is presented. The design, which provides a way of detecting faults and correcting errors in RAMs within milliseconds while concurrently performing normal execution of programs, is reviewed. The approach is to add two parity bits to each row in the storage arrays of the RAM chips and to provide hardware scrubbing interleaved with normal program cycles. The RAM and MIBB (memory interface building block) chip designs, and some of the augmentations and changes required from the original conceptual design, are examined. The approach has been determined to be feasible, and the three-year design process has also demonstrated the large distance between a conceptual design and its realization. Errors and deficiencies were found in the original design and corrected, and new useful functions were identified and added.<>