DocumentCode
3549731
Title
Diagnosis and failure analysis for scan failure
Author
Song, Z.G. ; Neo, S.P. ; Tun, T. ; Oh, C.K. ; Lo, K.F.
Author_Institution
Chartered Semicond. Manuf. Ltd., Singapore
fYear
2005
fDate
27 June-1 July 2005
Firstpage
181
Lastpage
184
Abstract
This paper describes a scan test that is widely used for microelectronic devices nowadays, and scan failure that is often ranked as one of the highest yield loss for most microelectronic devices. Due to its nature, the fault isolation of scan failure can´t be achieved by conventional current-based fault isolation techniques. So, establishment of scan failure diagnosis capability is very important. The four cases showed in this paper demonstrated that the scan failure could be diagnosed by diagnosis software effectively and various types of defects could be found by this methodology.
Keywords
automatic test software; boundary scan testing; failure analysis; fault diagnosis; automatic test pattern generation; failure analysis; microelectronic devices; scan failure diagnosis; software-based diagnosis; Automatic test pattern generation; Automatic testing; Circuit testing; Failure analysis; Flip-flops; Latches; Logic devices; Logic testing; Microelectronics; Software testing;
fLanguage
English
Publisher
ieee
Conference_Titel
Physical and Failure Analysis of Integrated Circuits, 2005. IPFA 2005. Proceedings of the 12th International Symposium on the
Print_ISBN
0-7803-9301-5
Type
conf
DOI
10.1109/IPFA.2005.1469157
Filename
1469157
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