• DocumentCode
    3549732
  • Title

    A reliable failure analysis methodology in analyzing the elusive gate-open failures

  • Author

    Remo, Nilda C. ; Fernandez, Jean Carla M

  • Author_Institution
    Fairchild Semicond. Philippines, Inc., Lapu-Lapu, Philippines
  • fYear
    2005
  • fDate
    27 June-1 July 2005
  • Firstpage
    185
  • Lastpage
    189
  • Abstract
    Gate-open failures are typically caused by physical disconnections within the various gate contact interfaces inside the package such as gate lead post to wire bond, die bond pad to wire bond, or within the gate wire itself. Various challenges surround the analysis of gate-open failures. Among others are the electrical difficulty, the intermittent nature of the failure, electrical overstress clouding the gate-open failure mechanism, and uncertainties on the destructive chemical decapsulation process, which is sometimes doubted as a defect contributor. This makes the failure elusive and misleading, at times resulting to erroneous analysis. This paper aims to present a reliable failure analysis methodology in analyzing the elusive gate-open failures. An approach consisting of specially designed series of previously established failure analysis techniques and used in conjunction with a gate-open curve trace testing method by Palermo and Moreno. Actual case studies utilizing the mentioned approach are used to demonstrate the application of the methodology.
  • Keywords
    contact resistance; delamination; electronics packaging; electrostatic discharge; failure analysis; integrated circuit bonding; interface phenomena; reliability; destructive chemical decapsulation process; electrical difficulty; electrical overstress clouding; erroneous analysis; failure analysis techniques; gate contact interfaces; gate-open curve trace testing method; gate-open failure mechanism; physical disconnections; reliable failure analysis methodology; Bonding; Chemical analysis; Chemical processes; Cities and towns; Contacts; Earth Observing System; Failure analysis; Packaging; Testing; Wire;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Physical and Failure Analysis of Integrated Circuits, 2005. IPFA 2005. Proceedings of the 12th International Symposium on the
  • Print_ISBN
    0-7803-9301-5
  • Type

    conf

  • DOI
    10.1109/IPFA.2005.1469158
  • Filename
    1469158