Performance of super-critical strained-Si directly on insulator (SC-SSOI) CMOS based on high-performance PD-SOI technology

Author

Thean, A.V.-Y. ; White, T. ; Sadaka, M. ; McCormick, L. ; Ramon, M. ; Mora, R. ; Beckage, P. ; Canonico, M. ; Wang, X.-D. ; Zollner, S. ; Murphy, S. ; Pas, V. Van Der ; Zavala, M. ; Noble, R. ; Zia, O. ; Kang, L.-G. ; Kolagunta, V. ; Cave, N. ; Cheek, J.

Author_Institution

Freescale Semicond. Inc, Austin, TX, USA

fYear

2005

fDate

14-16 June 2005

Firstpage

134

Lastpage

135

Abstract

This paper describes the performance of multiple-V_T, Triple-gate oxide SC-SSOI CMOS realized with Freescale´s high-performance silicon-on-insulator (HiPerMOS-SOI) and SOITEC´s advanced wafer-bonding technology. The thermal stability of wafer-bonded strained substrate, the beneficial impact of biaxial strain on gate-leakage and SC-SSOI enhanced SRAM bitcell operation are demonstrated for the first time. In-addition, the important scaling issues due to parasitic resistance and channel strain engineering are identified.

Keywords

CMOS integrated circuits; SRAM chips; electric resistance; leakage currents; silicon-on-insulator; substrates; thermal stability; wafer bonding; PD-SOI technology; SC-SSOI CMOS; SRAM bitcell; biaxial strain; channel strain engineering; gate-leakage; high-performance silicon-on-insulator; parasitic resistance; strained-Si directly on insulator; thermal stability; triple-gate oxide; wafer-bonded strained substrate; wafer-bonding technology; CMOS technology; Capacitance; Capacitive sensors; Displays; Doping; Insulation; MOS devices; Silicon on insulator technology; Tensile strain; Threshold voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, 2005. Digest of Technical Papers. 2005 Symposium on

Print_ISBN

4-900784-00-1

Type

conf

DOI

10.1109/.2005.1469242

Filename

1469242