A novel locally engineered (111) V-channel pMOSFET architecture with improved drivability characteristics for low-standby power (LSTP) CMOS applications

Author

Weber, O. ; Scheiblin, P. ; Ritzenthaler, R. ; Ernst, T. ; Andrieu, F. ; Ducroquet, F. ; Damlencourt, J.F. ; Le Tiec, Y. ; Papon, A.M. ; Dansas, H. ; Brévard, L. ; Toffoli, A. ; Guillaumot, B. ; Deleonibus, S.

Author_Institution

CEA-DRT-LETI, Grenoble, France

fYear

2005

fDate

14-16 June 2005

Firstpage

156

Lastpage

157

Abstract

We report a locally engineered high mobility (111) Si channel pMOS architecture with a HfO₂/TiN gate stack on a bulk standard [001] substrate. A 50% hole mobility enhancement and an integration density improvement compared to co-integrated [001] planar devices is demonstrated. An I_on (210μA/μm)/I_off (8pA/μm) ratio @Vdd=1.2 V is obtained (EOT=1.65nm), exceeding the previously reported LSTP performance in sub-0.1 μm high-k gated pMOSFETs.

Keywords

MOSFET; annealing; atomic layer deposition; dielectric thin films; etching; hafnium compounds; hole mobility; photolithography; silicon; titanium compounds; 1.2 V; 1.65 nm; HfO₂; TiN; V-channel pMOSFET architecture; annealing; atomic layer deposition; dielectric thin films; drivability characteristics; etching; high mobility pMOS architecture; hole mobility enhancement; integration density improvement; low-standby power CMOS applications; photolithography; Chemical vapor deposition; Etching; Hafnium oxide; High K dielectric materials; High-K gate dielectrics; Leakage current; MOSFET circuits; Microstrip; Power engineering and energy; Tin;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, 2005. Digest of Technical Papers. 2005 Symposium on

Print_ISBN

4-900784-00-1

Type

conf

DOI

10.1109/.2005.1469249

Filename

1469249