• DocumentCode
    3549935
  • Title

    Experimental verification of row-by-row variable VDD scheme reducing 95% active leakage power of SRAM´s

  • Author

    Saliba, Fayez Robert ; Kawaguchi, Hiroshi ; Sakurai, Takayasu

  • Author_Institution
    Sch. of Eng., Tokyo Univ., Japan
  • fYear
    2005
  • fDate
    16-18 June 2005
  • Firstpage
    162
  • Lastpage
    165
  • Abstract
    Low-power SRAM has become a critical component in recent VLSI systems. This paper reports an SRAM reducing 95% of active leakage power. The SRAM is successfully implemented and reliably measured for the first time, with self-aligned timing generation to avoid malfunction during VDD transition. The cycle time overhead is 9%, and the area overhead is 3.5%.
  • Keywords
    SRAM chips; VLSI; electrical faults; SRAM; VLSI system; active leakage power; experimental verification; low active leakage; low power; row-by-row variable VDD scheme; self-aligned timing generation; Circuits; Collaboration; Power engineering and energy; Power system reliability; Proposals; Random access memory; Time measurement; Timing; Very large scale integration; Voltage;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Circuits, 2005. Digest of Technical Papers. 2005 Symposium on
  • Print_ISBN
    4-900784-01-X
  • Type

    conf

  • DOI
    10.1109/VLSIC.2005.1469356
  • Filename
    1469356
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3549935