DocumentCode
3549961
Title
A self-tuning DVS processor using delay-error detection and correction
Author
Das, Shidhartha ; Pant, Sanjay ; Roberts, David ; Seokwoo Lee ; Blaauw, David ; Austin, Todd ; Mudge, Trevor ; Flautner, Krisztian
Author_Institution
Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA
fYear
2005
fDate
16-18 June 2005
Firstpage
258
Lastpage
261
Abstract
In this paper, we present the implementation and silicon measurements results of a 64bit processor fabricated in 0.18μm technology. The processor employs delay-error detection and correction scheme called Razor to eliminate voltage safety margins and scale voltage 120mV below the first failure point. It achieves 44% energy savings over the worst case operating conditions for a 0.1 % targeted error rate at a fixed frequency of 120MHz.
Keywords
error correction; error detection; flip-flops; integrated circuit design; logic design; microprocessor chips; 0.18 micron; 120 MHz; 64 bit; Razor; delay error correction; delay error detection; dynamic voltage scaled processor; failure point; self tuning DVS processor; voltage safety margin; Delay; Detectors; Dynamic voltage scaling; Error analysis; Flip-flops; Latches; Metastasis; Signal restoration; Silicon; Voltage control;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Circuits, 2005. Digest of Technical Papers. 2005 Symposium on
Print_ISBN
4-900784-01-X
Type
conf
DOI
10.1109/VLSIC.2005.1469380
Filename
1469380
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