A 6GS/s, 4-bit receiver analog-to-digital converter with embedded DFE

Author

Varzaghani, Aida ; Yang, Chih-Kong Ken

Author_Institution

California Univ., Los Angeles, CA, USA

fYear

2005

fDate

16-18 June 2005

Firstpage

322

Lastpage

325

Abstract

A 4-bit 6GS/s A/D converter is designed for a serial-link receiver and features an embedded adjustable one-tap DFE. Feedback-delay is relaxed through applying DFE to a 10-way interleaved pipelined architecture. Code-overlapping is used to remove residual ISI. Measured performance at 6GS/s shows 22.5dB of low-frequency input SNDR. DFE tap-coefficient is adjustable from 0 to 0.25 with 6-bits of programmable weight. The 1.8×1.6mm² chip is fabricated in 0.18μm CMOS technology and consumes 780mW at 1.8V power-supply.

Keywords

CMOS digital integrated circuits; analogue-digital conversion; decision feedback equalisers; embedded systems; integrated circuit design; intersymbol interference; radio receivers; 0.18 micron; 1.8 V; 4 bit; 780 mW; A/D converter; CMOS technology; analog-to-digital converter; code-overlapping; decision feedback equalizer; embedded DFE; feedback-delay; interleaved pipelined architecture; residual intersymbol interference; serial-link receiver; signal-to-noise ratio; Analog-digital conversion; CMOS technology; Clocks; Decision feedback equalizers; Delay; Intersymbol interference; Pipeline processing; Semiconductor device measurement; Signal resolution; Signal to noise ratio;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Circuits, 2005. Digest of Technical Papers. 2005 Symposium on

Print_ISBN

4-900784-01-X

Type

conf

DOI

10.1109/VLSIC.2005.1469396

Filename

1469396