0.5 V asymmetric three-Tr. cell (ATC) DRAM using 90nm generic CMOS logic process

Author

Ichihashi, Motoi ; Toda, Haruki ; Itoh, Yasuo ; Ishibashi, Koichiro

Author_Institution

Semicond. Technol. Acad. Res. Center, Kanagawa, Japan

fYear

2005

fDate

16-18 June 2005

Firstpage

366

Lastpage

369

Abstract

Asymmetric three-Tr. cell (ATC) DRAM which has one P-and two N-MOS transistors for one unit cell is proposed with "forced feedback sense amplifier" and "write echo refresh". Memory array of ATC DRAM operates at 0.5V and use only logic process with no additional process. A test chip on 90 nm technology dissipates 180 μA in refresh current at 1 μs cycle refresh on 1Mb with SG mode.

Keywords

CMOS logic circuits; CMOS memory circuits; DRAM chips; integrated circuit design; low-power electronics; 0.5 V; 1 mus; 180 muA; 90 nm; ATC DRAM; CMOS logic process; NMOS transistor; PMOS transistor; SG mode; asymmetric three-Tr. cell; cycle refresh; forced feedback sense amplifier; memory array; refresh current; test chip; unit cell; write echo refresh; CMOS logic circuits; CMOS process; CMOS technology; Circuit testing; Leakage current; Logic testing; Power supplies; Random access memory; Subthreshold current; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Circuits, 2005. Digest of Technical Papers. 2005 Symposium on

Print_ISBN

4-900784-01-X

Type

conf

DOI

10.1109/VLSIC.2005.1469406

Filename

1469406

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3549989