Methods of isolation of active elements in integrated circuits

Two basic techniques for the isolation of active elements within a monolithic silicon planar integrated circuit are described. The first method consists of placing back-biased silicon diodes between each active element. The high impedance of the silicon junction below breakdown voltage acts as the isolating element. This impedance is frequency dependent, since the junction has a parasitic capacitance associated with it. This parasitic capacitance limits circuit performance at very high frequencies. The second method of isolation involves forming the active elements within a high resistivity silicon substrate. The high sheet resistance of the substrate is used to form regions of high impedance between the active elements. This impedance is not frequency dependent and circuit performance at high frequencies is not limited by this isolation scheme.