Design, fabrication and performance of a 1024-bit bucket-brigade shift register

In order to provide a general-purpose dynamic shift register, and to demonstrate the LSI capabilities of the bucket-brigade class of MOS circuits, a 1024-bit bucket-brigade dynamic shift register chip has been designed and built. This chip is organized as four 256-bit registers with common clocking. It operates up to 1 MHz with a 10 V p-p clock swing. Digital regeneration has been included at 16-bit intervals to offset the degradation of incomplete charge transfer at high frequencies. The design has been based on the Al2O3-SiO2insulated gate FET technology, including the use of BIGFET´s to supply the output currents required to interface with TTL circuits. The chip is 0.167 inches beam-tip to beam-tip, and the effective area of each bucket-brigade bit is 10.8 square mils using 10µ design rules and oversized cell size to provide wide operating margins. On a few test slices, the operating frequency has been extended from the normal 1 MHz to at least 1.5 MHz by the inclusion of an ion implant to control dynamic drain conductance.