A 4096 bit offset gate CCD: Some experimental results

The offset gate approach for producing high density charge coupled device arrays was introduced at the 1973 International Electron Devices Meeting. The purpose of this talk is to describe progress made with this structure during the past year. A 4096 bit series-parallel-series memory array has been designed and tested. Table 1 is presented to summarize the dimensional characteristics of the design. Table 2 lists some of the implementation characteristics. The effective fast surface state density, Nss was found to be consistent with measured transfer efficiency using analysis techniques described in the literature. Based on an N_ss of about 7 x l0^l0/(cm² ev) the models cited indicate that the parallel edge loss is the greatest contributor to the measured transfer loss of 2 x l0^-3. Yield data on several lots of these 4096-bit memory arrays have been encouraging, with no systematic process related defects apparent. In conclusion, the 4096 bit SPS array has provided information indicating the viability of the offset gate te.chnique for making high density CCD arrays with predictable transfer characteristics and yield.