VLSI microprocessor design for classroom instruction

Author

Varrientos, Joseph E. ; Rys, Andrzej

Author_Institution

Dept. of Electr. Eng., Texas A&M Univ., College Station, TX, USA

fYear

1991

fDate

12-14 Jun 1991

Firstpage

70

Lastpage

75

Abstract

An outline for the instruction of VLSI microprocessor design is given. Considerable preplanning and complexity reduction by use of hierarchy is proposed to simplify the design procedure and reduce or eliminate design iterations late in the design. The microprocessor designed is a modified version of a simple-instruction accumulator machine designed for teaching software and hardware concepts. The design beings with the construction of standard cell libraries using the CAD tools VIVID and MAGIC. A design in VIVID is supported to verify circuit functionality, and a design in MAGIC is supported for final layout. The design continues with considerations for arithmetic-logic-unit (ALU) design, clocking schemes, bus-pre-charging, floorplanning, system timing, and interfacing to memory

Keywords

VLSI; circuit CAD; logic CAD; microprocessor chips; teaching; CAD tools; MAGIC; VIVID; VLSI microprocessor design; arithmetic-logic-unit; bus-pre-charging; circuit functionality; classroom instruction; clocking schemes; complexity reduction; design iterations; design procedure; final layout; floorplanning; interfacing; preplanning; simple-instruction accumulator machine; standard cell libraries; system timing; teaching; Circuits; Clocks; Design automation; Education; Hardware; Microprocessors; Software design; Software libraries; Timing; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

University/Government/Industry Microelectronics Symposium, 1991. Proceedings., Ninth Biennial

Conference_Location

Melbourne, FL

ISSN

0749-6877

Print_ISBN

0-7803-0109-9

Type

conf

DOI

10.1109/UGIM.1991.148124

Filename

148124