Electrically alterable programmable logic array (EAPLA)

A functional Electrically Alterable Programmable Logic Array (EAPLA) has been developed to serve as fast turn-around-time engineering hardware for custom structured macro design in VLSI. A novel electrically alterable, floating gate memory device has been developed with double polysilicon technology. It was used in the PLA array such that the personalization patterns of the PLA can be electrically altered in the users´ laboratory after packaging. The non-volatile memory device employs channel hot electron injection to write and junction avalanche breakdown hot hole injection or Fowler-Nordheim electron tunneling across the oxides to erase. Unique features of the cell structures and implementation to the EAPLA will be discussed.