• DocumentCode
    3555284
  • Title

    Triple level polysilicon E2PROM with single transistor per bit

  • Author

    Kupec, J. ; Gosney, W.M. ; McKenny, V. ; Kowshik, V.

  • Author_Institution
    Mostek Corporation
  • Volume
    26
  • fYear
    1980
  • fDate
    1980
  • Firstpage
    602
  • Lastpage
    606
  • Abstract
    An electrically-erasable, floating-gate PROM cell utilizing three levels of polysilicon is described. The cell is programmed via a channel injection mechanism similar to EPROMS. Erasure is accomplished with the third level of polysilicon which serves as an erase electrode causing field emission of electrons from the edges of the floating-gate. Conventional NMOS processing is used and all oxides are thicker than 800A. An adaptive erase feature is used to prevent over erasure into depletion and eliminates the requirement of a gating or series enhancement transistor. Endurance (ability to program and erase repeatedly), of a single cell is greater than 1000 cycles and is limited by electron trapping. Data retention has been experimentally determined to be comparable to EPROMs (greater than 10 years).
  • Keywords
    Charge carrier processes; Circuits; Degradation; Electrons; Impedance; Nonvolatile memory; Packaging; Photoelectricity; Region 3; Voltage;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electron Devices Meeting, 1980 International
  • Type

    conf

  • DOI
    10.1109/IEDM.1980.189905
  • Filename
    1481348