A wafer scale programmable systolic data processor

Author

Landis, Dave ; Yoder, Joe ; Whittaker, Denny ; Dobbins, Tim

Author_Institution

Center for Microelectron. Res., Univ. of South Florida, Tampa, FL, USA

fYear

1991

fDate

12-14 Jun 1991

Firstpage

252

Lastpage

256

Abstract

The authors describe the programmable systolic data processor (PSDP). The PSDP will enhance US Department of Defense (DoD) mission capabilities by extending signal and data processing speed/performance while reducing system size, weight, and power consumption. The characteristics of this architecture which make it opportune for building as a wafer-scale system include broad homogeneity, ease of redundancy, and limited physical interconnect bandwidth of wafer-scale integration (WSI) using a robust programmable systolic array processing architecture. Thus, it will provide unique onboard processing capabilities for DoD missions

Keywords

CMOS integrated circuits; VLSI; microprocessor chips; systolic arrays; CMOS; DoD mission capabilities; WSI; ease of redundancy; homogeneity; limited physical interconnect bandwidth; onboard processing; programmable systolic data processor; systolic array processing architecture; wafer-scale integration; wafer-scale system; Aerospace electronics; Computer architecture; Energy consumption; Microelectronics; Power system interconnection; Random access memory; Read-write memory; Signal processing; Signal processing algorithms; Throughput;

fLanguage

English

Publisher

ieee

Conference_Titel

University/Government/Industry Microelectronics Symposium, 1991. Proceedings., Ninth Biennial

Conference_Location

Melbourne, FL

ISSN

0749-6877

Print_ISBN

0-7803-0109-9

Type

conf

DOI

10.1109/UGIM.1991.148160

Filename

148160