The constrained via minimization problem for PCB and VLSI design

A novel via minimization approach is presented for two-layer routing of printed-circuit boards and VLSI chips. The authors have analyzed and characterized different aspects of the problem and derived an equivalent graph model for the problem from the linear-programming formulation. Based on the analysis of their unified formulation, the authors pose a practical heuristic algorithm. The algorithm can handle both grid-based and gridless routing. Also, an arbitrary number of wires is allowed to intersect at a via, and both Manhattan and knock-knee routings are allowed.<>