WOS: Low-resistance self-aligned source, drain and gate transistors

Device scaling leads to high resistance interconnects for both polysilicon and diffusion lines. The use of low temperature plasma deposited silicon nitride combined with selective tungsten deposition yields a process that is compatible with both low interconnect resistance requirements and standard polysilicon gate technology. Low interconnect resistance (1Ω) and low contact resistance (< 5× 10^-7Ω cm²) to polysilicon and diffusion have been obtained using the process flow described in this paper. Reduced temperature cycles at the end of the process and elimination of phosphorous in the interlayer dielectric make this process ideal for high density, high reliability VLSI applications.