Analysis of latchup susceptibility in CMOS circuits

The traditional npn- pnp transistor model for CMOS latchup does not adequately describe the performance of modern epitaxial devices, especially when holding voltage is in excess of one volt. In this paper, a model is discussed which correctly represents bulk ohmic voltage drop in the latchup region near the surface of epitaxial devices. Analysis of this model indicates that, for sufficiently thin epitaxial layers, tank contact placement is the most important factor in producing latchup free devices with holding voltage greater than the power supply voltage. Effects of substrate, bias are also discussed, and it is concluded that although holding voltage is increased by application of substrate bias. use of an on-chip charge pump to provide the bias can produce undesirable cumulative transient effects.